Semiconductor memories can generally be divided into two groups--volatile and non-volatile. The first group is used far more frequently than the second. It employs dynamic or static logic elements and techniques to store bits of data in a pattern which can be changed externally almost any number of times (typical number of "write" cycles where the information in a cell is changed exceeds 1.times.10.sup.14). The main problem with this group, of which two examples appear in FIGS. 1 and 1a is that memory storage is volatile, that is, power must be constantly applied to each memory cell to avoid loss of memory. Even though some advanced designs require very little power for memory retention, battery backup must still be used to provide for a possible power failure. Examples of such memories are the one-transistor-per-cell dynamic RAM (Random Access Memory) and the six-transistors-per-cell static RAM.
The second group of memories relies on special MOS devices to retain information for very long periods of time (on the order of tens of years) even with power removed. This is usually achieved by application of high voltage pulses to the gate or drain of the specially constructed transistor, which achieves through transfer and trapping of electric charges a semipermanent change of the transistor threshold voltage. The memory state is determined by the magnitude of this threshold voltage. The main problem with this group of memories is that the high voltage stressing required for writing (or erasing) rapidly degrades the memory device (a phenomenon known as "cycling fatigue"). Therefore, its threshold state can be changed only a limited number of times, typically 1.times.10.sup.6 cycles. As such it is useful as a read-only or read-mostly memory, but not as a read/write memory. A further limitation of existing non-volatile memories such as MNOS (Metal-Nitride-Oxide-Semiconductor) and FAMOS (Floating Gate-Avalanche Injection MOS) is that writing of the non-volatile memory state requires relatively high voltage pulses and that they are slow, taking typically 1 to 10 msec to write each bit of information. This problem is greatly alleviated in a related non-volatile memory device disclosed by the present applicant in an application filed on Mar. 26, 1976 in the U.S. Patent Office Ser. No. 671,183 now U.S. Pat. No. 4,110,533. In this memory device write and erase operations are much more efficient, and result in write or erase high voltage pulse times of typically 1 to 10 .mu.sec. However, these new memory transistors still suffer to some extent from cycling fatigue and would therefore not be used in applications other than where a read-only or read-mostly memory is required.
By incorporating the non-volatile memory transistors of the second group in a volatile memory cell of the first group it is possible to achieve a superior memory cell having the write/read characteristics of the first group and the non-volatility of the second group. This is basically a read/write volatile RAM where each memory cell is backed up by a second level of non-volatile memory element.
The most closely related prior art devices rely on MNOS variable threshold transistors to achieve non-volatility for the memory cell. One such prior art cell and its method of operation is described in U.S. Pat. No. 3,831,155 and is shown in FIG. 1b.
The same latch is described in an article "Memory Cells for N-Channel MNOS Arrays", presented at the Non-Volatile Memory Conference held in Vail, Colo. on August 1976 by F. Schuermeyer and C. Young from the Air Force Avionics Lab. The related memory cell described by these authors is named Static VINRAM (Virtual Non-Volatile RAM) and is shown in FIG. 1b, herein. The following brief description of that circuit is based on the article.
Q.sub.1 and Q.sub.3 are depletion mode MNOS transistors which are in the high conduction state for volatile operation. In the volatile mode the operation of the cell is identical to that of the volatile cell described by J. M. Schlageter et al, "A 4K STATIC 5V RAM", ISSCC 1976, paper 12.5, shown herein in FIG. 1a, with V.sub.GG =V.sub.SS. In order to transfer information stored in the volatile mode to information stored in the non-volatile mode or, in other words, to permanently store information which was previously stored so that it was subject to erasure in case of a power failure, a +25 volt 1 msec pulse is applied to the V.sub.GG line in FIG. 1b. Assuming that Q.sub.3 is conducting and that consequently node A=V.sub.SS and node B=V.sub.DD=+ 10 volts, the pulse so applied will cause the source of Q.sub.1 to remain at V.sub.SS and consequently the total gate voltage to drop across its insulator, switching Q.sub.1 into the low conduction (high threshold) state. Since the source and drain of Q.sub.3 are both at the +10 volt potential, a depletion layer forms in Q which inhibits the writing of Q.sub.3, causing it to remain in the high conduction state. In order to recover information stored in the non-volatile mode, +10 volts is applied to the drains of Q.sub.1 and Q.sub. 3 (V.sub.DD). Since Q.sub.3 is in the high conduction state, node B will rise faster than node A, thus resetting the flip flop to its original position. After the flip flop has been set, Q.sub.1 and Q.sub.3 should both be erased. In order not to lose the volatile data, erasure should be performed with many short erase pulses (-25 volts gate-to-substrate) rather than one long pulse.
It is quite apparent that the FIG. 1b memory cell, while possessing the desired characteristics of a non-volatile read/write memory, is rather difficult to operate favorably because of the need for both positive and negative high voltage pulses to be applied to the chip to achieve the non-volatility feature. Further, as pointed out by Schuermeyer and Young, the erase operation must be carefully performed through a series of many short pulses at a high voltage (-25V), which in turn can result in unpredictable voltage and current spikes in different parts of the LSI chip, with possible, and difficult to predict, loss of the volatile data. The main problem is clearly due to the fact that each non-volatile writing operation must be followed by an erase operation before the next non-volatile write operation can be performed. The reason for this can be explained by examining a typical case for the memory cell of FIG. 1b. Assume that initially no information is written into the non-volatile mode. Then the two MNOS transistors Q.sub.1 and Q.sub.3 are in their high conduction state, both with thresholds of typically -5V. When the +25V 1 msec pulse is applied to their gates in order to transfer the information from the volatile to non-volatile mode, it will cause one of the two, say Q.sub.1 to change its threshold to typically +2V, leaving the threshold of Q.sub.3 unchanged. If the volatile state (or information content) of the latch were now changed to opposite its initial state, it would not be possible to transfer this new information into the non-volatile mode because application of the +25V 1 m sec pulse would simply result in Q.sub.3 changing its threshold to +2V, with Q.sub.1 remaining at +2V. In this new state, since both MNOS transistors have equal thresholds of approximately +2V, it is not possible to distinguish the last volatile state written into the latch. For this reason it is necessary to condition each memory cell to the MNOS low threshold (high conduction) state before each new non-volatile write operation so that only one of the two MNOS transistors will go to the high threshold state.
This conditioning by erasing all MNOS transistors is problematic because the high voltage negative pulses turn both MNOS load transistors Q.sub.1 and Q.sub.3 off, thereby cutting off power to the latch. Therefore, it is necessary to apply these -25 volt pulses in short bursts relying on contunuous storage on the capacitances of nodes A and B during the time the pulses are applied. A further problem with this approach is that for a large memory array employing the cells of FIG. 1b, the very large capacitive drive required to bring V.sub.GG up to +25 volts or -25 volts mandates a direct line to external drive circuitry, exposing any of the several thousand MNOS load transistors to static charge which, even if it will not cause outright shorts will, in any case, result in very large and unpredictable threshold shifts randomly distributed across the array. Furthermore, it may be altogether impossible to apply -25 volt and +25 volt pulses for short durations uniformly across the entire memory array. That is, because of the capacitances and resistances along the V.sub.GG line, some parts of this line will rise faster than others or reach a voltage closer to -25 volts or +25 volts than other parts so that erase or write will not be uniform across the entire array.
It is therefore a principal object of the present invention to provide a semiconductor latch circuit which is capable of either volatile or non-volatile information storage.
A more specific object of the invention is to provide such a circuit wherein the status of stored data may be changed from volatile to non-volatile by applying a single pulse thereto and without any need for an intermediate erase operation between successive non-volatile write operations.
These and other objects of the invention are attained by an integrated semiconductor latch circuit having a pair of branches, each including an insulated gate field effect transistor (IGFET) load and an IGFET driver connected in series drain to drain at a node. The control gate of the IGFET driver of each branch is cross-connected to the node of the other branch in order to provide a latch circuit capable of volatile information storage. Non-volatile information storage in accordance with the present invention is made possible by making the threshold voltage of at least one of the IGFETs electrically variable, preferably but not necessarily by providing it with a floating gate having a thin oxide area over the node to which the IGFET is connected. An IGFET having such a floating gate will hereinafter be referred to as a FATMOS (Floating Gate Thin Oxide Tunneling) transistor and the resulting latch circuit will be referred to as a NOVRAM (Non-volatile Random Access Memory) latch. A NOVRAM latch in accordance with the present invention may have either a pair of variable threshold drivers in combination with a pair of fixed threshold IGFET loads or alternatively a pair of fixed threshold IGFET drivers combined with a pair of variable threshold transistor loads. In either case volatile information storage is accomplished by normally maintaining a supply voltage across both branches which is below that required to change the thresholds of the variable threshold transistors and by turning on one or the other driver so as to set the latch in one of its two stable states. The latch will remain in that state so long as the required supply voltage continues to be applied across its branches.
To permanently store the volatile information in non-volatile form the supply voltage previously applied across the two branches of the latch is briefly raised to a higher level which is sufficient to change the thresholds of the variable threshold transistors. This will result in equal but opposite threshold shifts in the two variable threshold transistors so that, if power is removed from the latch after the non-volatile writing operation, the information which had been stored in the latch prior to that operation will be retained in the form of their threshold shifts. When power is next applied to the latch the branch containing the transistor whose threshold was lowered will turn on first and will cause the other variable threshold transistor to be turned off, an effect which will be reinforced by the increased threshold level of that other FATMOS transistor.
In some applications a latch as described might have excessive current drain for reasons which will be explained in greater detail hereinafter. Basically, such current drain might be due to the fact that during non-volatile writing when the high voltage pulse is applied to bring about a threshold shift in the variable threshold transistors, one of them may be shifted into a negative threshold state in which the device will conduct even when a zero bias is applied to its control gate (depletion mode operation). In accordance with a further object and feature of the present invention this drawback is eliminated by adding an additional IGFET, whose threshold remains constant, in series with each of the variable threshold transistors. Consequently, even when a particular variable threshold transistor has its threshold shifted into depletion mode operation, the branch containing it will be prevented from drawing excessive current by the additional constant threshold transistor which will not be biased into conduction at the same time.
A further specific object and feature of the present invention is to simplify the basic NOVRAM latch circuit by using a variable threshold transistor in only one of its branches to achieve non-volatility, rather than to use one in each branch.
Use of only a single variable threshold transistor per NOVRAM latch results in significantly improved yields, particularly when that transistor is a FATMOS, since the thin tunneling oxide between the floating gate and the substrate of a FATMOS transistor is a major yield reducing factor, particularly in very large memory arrays. By using only one FATMOS transistor per latch instead of two, the total area of thin oxide for a given memory array is halved and so is the probability of a pinhole which could ruin an entire chip containing the memory array.
Yet another related object and accomplishment of the present invention is to improve upon the previously mentioned NOVRAM latch embodiments wherein the variable threshold transistor is a FATMOS by extending the floating gate of the variable threshold FATMOS transistor (typically the driver) into the channel region of its associated IGFET load which in this case will be of the opposite conductivity type. As a result, both the load and the driver will have a variable threshold which will shift by equal amounts as a result of a non-volatile (high supply voltage) write operation. Because the load and driver are of opposite conductivity types, the mutually reinforcing effect will be similar to that obtained by using one FATMOS transistor in each branch but will be achieved by using only a single thin tunneling oxide area. Thus, while this feature of the invention yields the performance advantages of the basic two-FATMOS transistor cell, it does so at a significantly higher yield, since it requires only a single tunneling oxide area per cell.